The 32 bit width of the 386 bus required a large number of memory chips if one bit wide DIP packages were used for memory. Memory modules with 256K or 1mb of byte wide memory quickly became popular. The 386DX required four byte wide memory modules to accommodate its 32 bit bus. The 2 to 8 megabit modules were expensive. To reduce low end system prices, Intel introduced a variant of the 386, the 386SX, with a 16 bit wide external bus and 16mb data space. Late in the lifetime of the 386,Intel released a 32 bit reduced power CPU, the 386SL. IBM demonstrated and possibly released a 386SLC with a small internal cache memory.
The 80386 memory management was far preferable to that of the 80286 but slowed many instructions somewhat. Despite improvements in individual instructions and the switch to a 32 bit external bus, the 386 was only modestly faster than the 80286 at the same speed. The 386DX was advertised as having a pipelined architecture, and as being capable of 4 to 6 MIPS. This indicates about 4 clocks per instruction -- a bit faster than an 80286 at the same clock speed. Intel claims that the 386DX was something less than twice as fast as an 80286 at the same clock speed. They rate the 386SX as being probably slightly slower than an 80286. As recently as 1998, Intel was stating that the 386DX was 11.4MIPS at 33MHz and the 386SX at 2.5 to 3 MIPS at any clock speed
(It is likely that the 386SX MIPS measurements made by Intel were done on a machine with performance that was memory limited rather than CPU limited. It is possible that all 386SX motherboards are memory limited. It is also possible that the measurement was poorly done.)
An 80387 math coprocessor was introduced with the 80386, but the 386, when used with a math coprocessor at all, generally was used with the older 80287 math coprocessor or with cheaper third party math coprocessors.
Return To Index Copyright 1994-2002 by Donald Kenney.