The original IBM PC was designed using a single eight channel 8259 Interrupt controller. The PC-AT cascaded an additional 8 channel 8259 onto IRQ2. The 16 (really 15 because one was used for the cascade) channels proved to be barely adequate. In the mid 1990s, the PCI Bus was introduced that allowed practical sharing of interrupts -- placing multiple interrupts on the same interrupt line and sorting them out in software. However, shared interrupts can have performance issues and even with sharing, 15 interrupt lines is not sufficient for multiple processors which would be very difficult to use with 8259 type controllers.
In the APIC architecture a CPU ("Local") APIC interface is connected to an APIC Bus. Most Pentium class CPUs have an internal APIC interface even though APIC systems were not developed for a number of years after the first Pentiums were released. In addition to the CPU APICs, there must be at least one IO-APIC on the bus that interfaces to I/O device interrupt lines. I/O APICs operate in parallel instead of cascading unit to unit as 8259s did. Up to eight I/O APICs are allowed. The theoretical limit of an I/O APIC is 64 interrupt signals. Current I/O APICs typically support only 24 lines. APIC Interrupt prioritization is handled by the hardware and does not require active software mediation as the 8259 does. Also unlike the 8259, prioritizing APIC interrupts does not require constant reprogramming the APIC interrupt controllers
APICs are not supported by MSDOS or Windows 9. They are supported by Linux, Windows NT, Windows 2000 and Windows XP. APICs are rarely found on single CPU motherboards and are always present on multiple CPU motherboards. Some single CPU motherboards allow a choice of APIC or 8259 Interrupt handling. When non-APIC OSes are used on motherboards that allow choices of APIC or 8259, the APIC interface must be disabled in the BIOS.
Return To Index Copyright 1994-2002 by Donald Kenney.