Conventional addressing requires that the CPU post an address which is then read by the memory. The memory accesses the data and (for reads) returns the data. This process requires at least 2 or 3 cycles (depending on whether one counts from the CPU or memory perspective) on non-clock multiplied CPUs. Burst Mode is used when data is being read from/written to sequential addresses. The initial address is provided by the CPU and subsequent addresses are provided by the memory and are clocked out at one word per cycle. Internal design considerations within the memory (interleaving) may dictate that it is more efficient not to generate output data in strict sequential order -- which is to say that words delivered might be address followed by address + 2 followed by address +1 followed by +3. Motorola and Intel use different bursting sequences meaning that burst RAM control is different for the two CPUs.
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