Common classical DRAMs are addressed breaking the address into two parts -- a column address and a row address. Two signals, RAS and CAS tell the DRAM which portion of the address is being presented. DRAM IC outputs are often 1 or 4 bits wide thus requiring memory to use 2 to 9 physical chips per byte. The only signals used other than address lines, CAS and RAS are data lines, Read/Write, and Output Enable which is used to couple the DRAM to data to the computer bus on read. There is no clock signal and no data ready signal from the DRAM. This means that the controlling circuitry must know/guess when data will be available.
There is nothing that prevents DRAM from being clocked, using broadside addressing or generating a data ready signal, but DRAM that does so doesn't run in sockets in wide use prior to about 1998. When 66MHz motherboards were introduced, many motherboards switched to a clocked DRAM -- SDRAM -- that uses classical DRAM internally, but uses a clock rather than timing of off CAS and RAS strobe signals.
The capacitors used in DRAM are very tiny and discharge in a few thousands of a second. Therefore the DRAM charge must be refreshed frequently. Fortunately all the capacitors accessible by a single column address (a page) can be refreshed in one operation.
Classical DRAM has two major timing parameters -- access time and recovery time. Access time is the time between presentation of an address to the DRAM and having the data available. This is the time generally associated with DRAM. Recovery time is roughly the same duration and is the time before the data can be accessed again. There are other delays, address multiplexing, data set up, etc. associated with DRAM access, but they are fairly short compared to access and recovery time. Many fast access time DRAM variants achieve the fast access by means of overlapped operations in separate internal banks and have poor initial access times. While any DRAM can be externally controlled in an array to support burst of operations from sequential addresses, some DRAMs have bursting built in. Sustained burst rate is the data rate for bursts of data from sequential addresses.
It has become popular to rate DRAMs in Megabits or Megabytes per second. These specifications are relatively worthless as it is rarely clear how wide a bus is being discussed and it is necessary to divide by the bus width to get to the more easily comparable MHz rating. I have used Mb/MB ratings only where I couldn't compute or find a MHz rating.
Since the advent of the Intel 386, DRAM access/recovery time has increasingly hindered computer performance. A number of schemes have been developed to improve DRAM performance. Data caching on motherboards and in CPUs -- avoids many DRAM references entirely.
Dual porting is used in applications like video. It allows data to be updated through one set of pins while different data is being read on other pins. Window RAM (WRAM) and VRAM are dual ported.
Several improvements have been made to classical DRAM over the years. All will operate in the same sockets, but most require chipset support to use advanced features. Clocked DRAMs introduced in the late 1990s requires different sockets.
Hidden refresh overlaps refreshing of one part of DRAM with data access to other parts. Most modern DRAMs support hidden refresh, but it is unlikely that most PC designs use the capability since its primary advantage would be in embedded systems.
Fast Page Mode saves the last page (everything accessible with one column address) inside the DRAM and allows fast access to data within that page. Most modern DRAMs support Fast Page Mode. Note that an access to data not in the current page may require a full precharge delay if fast page mode was in use. i.e. In some situations FPM may be slower than non-FPM.
Extended Data Out holds read data on the DRAM output pins while the CPU is posting the next address to be read on the address pins. EDO dram will run in non-EDO mode and thus can be used in older computers although it will not improve performance in those computers.
Caching holds frequently accessed data in fast storage in the DRAM. FPM is a primitive form of caching.
The following DRAM types were available/in work as of early 1999.
3D-RAM -- Appears to be like SDGRAM with broader logic capabilities and built in video manipulations. Peak transfer rates of 400MBits/second are claimed ("10 times the rate of Video RAM"). Mitsubishi. Shipping as of 3Q98. Capacity - 10Mbit. 32 bits wide. Burst rates - 200MHz read, 400MHz write (80/160nSec?). Latency - Not readily available. Presumably dismal, but may not be important in video applications.
Burst EDO (BEDO) is Extended Data Out DRAM which can operate in burst mode, generating addresses internally for sequential accesses once it has been presented with an initial address. Micron has announced an intention to produce burst EDO. Shipping? Specifications presumably will be similar to FPM.
Cache(d) DRAM (CDRAM) is DRAM with internal SRAM cache intended for Video applications. It is clocked and allows simultaneous access to cache and DRAM. Mitsubishi. Capacity - 16Mbit. 16 bits wide. Burst rates 66 to 100MHz (7 to 10 nSec) = 1 to 1.6Gbit/sec. Latency - Unknown.
CASn DRAM -- an alternate name for SDRAM. When using SDRAM, CAS 2 or 3 refers to CAS Latency (in clocks) which is a setting critical to high speed operation
Concurrent RDRAM -- RDRAM optimized to reduce the very long delays (several hundred nanoseconds) for return of the first data. It appears to be real and is being shipped by Samsung. No specifications found.
Double Rate DRAM - DRDRAM -- 64mb parts capable of 1.6GBit/Sec transfer rates are being sampled by Fujitsu, Hitachi, Mitsubishi
Extended Data Out (EDO) DRAM allows output data to be held on the data pins while the next address is being set up on the address pins. This saves one cycle on back to back non-burst reads (but not writes), EDO came into use in 1995-1996 and will probably eventually be found in all DRAM. See Burst EDO for Specifications. Current page hit access time is about 25nSec, page miss access time about 95nSec. Realistic bandwidths are around 220MBits per second.
Enhanced DRAM (EDRAM) uses internal SRAM caching and interleaving to speed up data access. It uses different signaling than ordinary DRAM and can not simply be plugged into an existing DRAM socket. It is produced by Ramtron, IBM and Enhanced Memory Systems. EMS products are claimed to have 10nsec Hit response, 25nSec page miss response and bandwidths around 600 Mbits per second.
EDO EDRAM is EDRAM with Extended Data Out. It is produced by Ramtron and will also be produced by IBM. It is not socket compatible with exiting DRAMs. See EDRAM for Timing
Enhanced Synchronous Burst DRAM (ESDRAM) is a burst DRAM with internal caching similar to EDRAM. It uses multiplexed addressing. As of early 1999 a 16Mbit part is being shipped by Enhanced Memory Systems. Claimed Latency is 12nSec from 22nSec DRAM. (sounds like two quarts of product in a 1 quart bag to me). Claimed bandwidth is around 800Mbits per second.
Fast Page Mode (FPM) DRAM -- Saves the most recently accessed page inside the DRAM. More or less the standard DRAM of the mid-1990s. Produced by many vendors. The following are specifications for premium FPM, EDO, and burst EDO DRAM. Many Vendors. Capacity -- 64MBit and bigger. 1, 2, 4, 8 or 16 bits wide. Burst rates to 22MHz (45nSec) -- typically a bit slower. Maximum latency about 90-120nSec.
IRAM -- Intelligent RAM -- DRAM with the CPU on chip. An academic initiative being widely investigated. Apparently initiated at UC Berkeley. Offers very great CPU to memory bandwidth. Unlikely to be used in PCs or other practical devices in the near future.
MultiBank DRAM -- MDRAM. From MoSys. An array of independent, simultaneously addressable 8k by 32 bit wide DRAM (or maybe 32K by 8bit wide -- documents say both, sometimes in the same document). MDRAM allows simultaneous access to different banks and features claimed initial access as quick as 20nSec with burst rates as fast as 6ns. MDRAM can be configured in small increments for special purpose functions. MDRAM appears to be used primarily in video applications. Being shipped by MoSys. No specifications found.
RAMbus -- (RDRAM) Single ported. Byte wide and broadside addressed with on chip bus control and interleave. RDRAM is not compatible with normal DRAM sockets. About 30% more expensive than DRAM. Perhaps 10-20% performance improvement in video applications. Toshiba and Samsung at least have shown samples of 16, 32 and 64Mbit parts in 1999. Rates to 800MHz are claimed, but actual specifications for shipping parts do not seem to be available.
RDRAM -- Son of Rambus. Intel's candidate for high speed memory in early 21st Century PC architectures. Capable of operating at 250MHz with two transfers per clock tick. It uses a 9 bit bus for an effective 500MBytes/Second. Uses bursts of up to 256 bytes for data transfer. Refer to RAMBus for details
RamLink/SyncLink. Another single ported byte wide, broadside addressed design. See SLDRAM.
Synchronous Burst SRAM. (SBSRAM) Static RAM, not DRAM, with clocking and pipelining built in.
Synchronous DRAM (SDRAM) Standard DRAM with built in clocking. Supports Burst Mode. Times specified are clock rates, not access time as is used with most other types of RAM. (i.e. 10 nSec SDRAM is 6 times as fast as 60nSec DRAM only if data can be retrieved in one clock -- which it can not.) On average, expect SDRAM to be a bit faster than DRAM -- because it is a newer design with some incremental improvements, not because it is inherently faster. [Note: As of early 1998, there were several incompatibilities between SDRAM DIMM designs and some motherboard/chipset designs. It is not clear that all these issues have been resolved]. Frankly specifications for these devices are a shambles. Realistic expectations seem to be 30 nsec (33MHz Burst operation using a 33, 66 or 100 MHz clock) with some claims of 20 nsec (50Mhz burst) operation.
Synchronous Graphics DRAM -- SGDRAM, SDRAM with block mode reads and writes and ability to mask portions of bytes during writes. Apparently being shipped and used in a few PC video cards. No specifications found.
Synchronous Graphics RAM (SGRAM). Dual banked clocked DRAM with block and masking capabilities designed for graphics operation at 100 to 166 MHz clocking. 200MHz operation is claimed. IBM is shipping 6.5nSec latency 128Kx32 bit wide parts capable of 150MHz bursts. Widely used in video and other specialty applications.
Synchronous Link DRAM - SLDRAM -- Probably a later term for Synchlink DRAM. Similar to SDRAM, but designed to an open standard. Heavily hyped as a competitor to RAMBus then suddenly vanished after the announcement that samples were shipping in 2ndQ98. A few press releases in late 1998 indicate that SLDRAM may still be alive. Specifications? No.
Synchronous Static RAM (SSRAM) SRAM, not DRAM, with activities synchronized to system clock.
SVRAM -- Synchronous VRAM -- Dual Port Video RAM with DRAM and Serial Access Memory (SAM) Buffering. with separate Refresh bus VRAM cycle time is in the 25nSec range and die size is 50% greater than comparable DRAM. Does not appear to be shipping or in use.
Video RAM (VRAM) Multi (usually dual) ported DRAM used for video applications. Widely used in both PCs and Macs, but I was unable to find a data sheet.
Virtual Channel Memory aka 64Bit Virtual Channel DRAM - (NEC/Siemans) Also Known as SDR DRAM -- possibly shipping around at about the end of 1999. Couldn't find either a data sheet or an explanation of the acronym SDR DRAM.
Window DRAM (WRAM or WDRAM) Internally simplified VRAM. Purportedly optimized for Windows operation and was hyped as being twice as fast as VRAM. In reality, it appears to be slightly faster and somewhat cheaper than VRAM. In use in at least one Matrox video card as of 1999.
My thanks to Scott Taylor for Reviewing the 1996 version of this.
Aside from data sheets on the semiconductor manufacturer web sites, the best web reference I have found is:
The following www document appears to be a very nice summary on DRAM -- unfortunately, my German is pretty weak
Return To Index Copyright 1994-2008 by Donald Kenney.