DRAM has several problems compared with SRAM. For one thing, the capacitors do not hold a charge forever. Even though the capacitor resistance is on the order of a million Megohms, the capacitors and charges are so small that they lose their charge in as little as a few tens of milliseconds. Reading the stored value depletes so much charge that the capacitor must be rewritten afterwards. Leakage is worked around by periodically recharging the capacitors. This is known as refreshing the DRAM. Another problem is that reading out the capacitors is a relatively time consuming process.
DRAM is rather slow compared to SRAM. As of 1999, the fastest raw access times for DRAM are around 25 nSec as compared to less than 10 nSec for SRAM.
The operation of a classical DRAM is fairly simple. The address is split into two parts - rows and columns. Each row is read out and written as a whole. This accomplishes two desirable things. First, by refreshing a whole row at one time it frees up enough time from refreshing to allow the device to actually be used for remembering things. Second, it decreases the number of pins and allows smaller packages to by used. Refreshing simply requires sending every possible row address to the DRAM often enough to ensure that the contents of the rows do not fade below detectability.
The Column address is used to identify a specific bit in the row. Both reads and writes require writing the contents of the row back to memory.
The intermediary between memory and the user is a set of "Sense Amplifiers" that temporarily hold the contents of the row while reads and writes progress.
The operation of a classical DRAM depends on 3 signals. Read/Write tells what kind of operation is in progress. Row Address Strobe (RAS) and Column Address Strobe (CAS) are used to control DRAM accessing. The basic operation is as follows:
1. When the RAS signal drops (it's active low), a group of memory cells (a row) is selected based on the address pins. Their contents are read into the sense amplifiers.
2. When CAS (also active low) drops, a specific sense amplifier is selected based on the address pins. If read is set, the contents are put on the data pin. If write is selected, the data pin value is written to the sense amplifier.
3. When CAS rises, the data pin is released.
4. When RAS rises, the contents of the sense amps are written back to memory.
If RAS is cycled without ever cycling CAS, the row will be read and written -- refreshed
A number of improvements have been made to DRAM over the years. One improvement grabs data from the sense amplifiers rather than going back to memory when accesses are made to the current row. This is known as Fast Page Mode and eliminates the time required to read out memory. It is accomplished by leaving RAS low and cycling CAS with a new address.
A second improvement places a refresh counter in the DRAM chip. This allows refreshing to be done without transmitting row addresses to the DRAM. Stepping the counter and refreshing is accomplished by cycling RAS while CAS is held low -- a signal combination that would not make sense in the classical DRAM. This is called hidden refresh and probably more often used in embedded systems than in PCs.
A third improvement holds read data on the output pin until the pin is used for something else. This is Extended Data Out which can save an occasional cycle during burst operations.
FPM, Hidden refresh, and EDO are backward compatible in that DRAMs that provide them may well run in systems designed for DRAMs that do not have the features.
Return To Index Copyright 1994-2002 by Donald Kenney.