Hamming Codes work by computing parities (Even parity as it happens) over subsets of the bits in a message. The subsets are cleverly selected so that an error in any bit produces a unique value in the Hamming Code. Four bit data is usually used as an example. Remembering that the code must detect failures in parity bits as well as failures in data bits, the four data bit code is computed of a seven bit "word" consisting of four data bits and three Hamming parity bits. Identifying the bits as D1,D2,D3,D4 and P1,P2,P3, the three parity bits are P1.D1.D2.D4, P2.D1,D3,D4, and P3.D2.D3.D4. If there is no error, the Hamming code will be 000. If P3 fails, the code will be 001. If P2 fails, the code will be 010. If D3 fails, the code will be 011, etc.
Hamming codes are identified by two numbers, the total word length and the number of data bits. The four bit code used above is a 7,4 code. The minimum number of Hamming parity bits is the number of bits used to identify the failed bit. Pragmatics dictate that Hamming Codes should fit into conventional multiples of 8 bit bytes. A 12,8 code is sometimes used with two data words per three bytes. For ECC memory, a 72,64 code is used which can be implemented as 8 9 bit words. Because PC designs often include parity, 9 bit words are familiar to PC designers. Computational considerations may cause the parity bits to be intermixed with the data bits in memory or data transmission, however, this intermixing will never be seen by the normal user.
Hamming Codes can correct single bit errors and detect 2 bit errors. Most three or more bit errors can be detected, but some will not be. In 1997, Intel started offering PC chipsets that permit ECC memory. It is claimed that ECC memory is as fast as conventional memory, however, it has been pointed out that writes of less that 64 bits or of non-aligned data require an extra read cycle to recompute the ECC code. Users have observed that ECC On/Off has no apparent affect on memory timing, and there is some conjecture that conventional memory might be unconditionally slowed to ECC timing in current chipsets.
There is considerable confusion over whether conventional 9 bit parity memory can be used in ECC mode with ECC chipsets. Apparently some motherboards are designed to support ECC with normal parity and can be set to operate in either Parity or ECC mode. Other motherboards require special ECC memory which does not support a parity mode.
Return To Index Copyright 1994-2002 by Donald Kenney.