The dual buses provide fully independent paths to the CPU and to the internal L1 cache. This architecture allows the L2 cache to be read and written without blocking the main memory bus and vice versa. This is important because without the dual bus structure, access to the L2 cache would be blocked frequently while the CPU waits for relatively slow operations on the Frontside Bus.
The backside bus will typically operate at a submultiple (1x, 1/2x, 1/3x, etc) of the CPU frequency. The frontside bus typically operates at a multiple (1x, 2x, 3x) of the PCI bus frequency.
Return To Index Copyright 1994-2002 by Donald Kenney.