ITANIUM

11/14/98

Itanium: Merced was Intel's code name for a 64 bit, 0.18 or 0.12 micron technology CPU planned to eventually replace the current (as of 1998) 32 bit designs. First scheduled for release in 1999, the current release date is mid-2000. Merced will use a Type-M socket. Conjecture is that Initial clock speeds might be around 600MHz moving on to 1GHz later.

The CPU will use a new -- non-80x8x 64 bit instruction set called IA-64 -- designed by Intel and HP and will include something called Explicitly Parallel Instruction Computing technology. it is claimed that EPIC will allow the programmer/compiler to specify what instructions are to be executed in parallel. That permits much speculative and control logic to be avoided in the CPU. In addition, Merced will feature a large number of registers (128) and will eliminate the hardware register pool and register renaming logic. Merced will be capable of speculative execution through branch instructions.

64 bits, incidentally, refers to the maximum data width, not the instruction length -- which is roughly 43 bits (three instruction groups in 128bit "bundles").

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