Memory Type Range Registers (MTRR). The MTRRs are externally programmable registers on Pentium Pro, Pentium 2 and later Intel CPUs. They are also present on some AMD CPU and VIA CPUs. Some Cyrix CPUs have address registers with a similar function. The number of registers varies on different CPUs. Although Intel claims 96 MTRRs for the Pentium 6, this turns out to be 88 fixed registers that map the first 1MB of memory with several different resolutions and 8 pairs of variable registers for all of memory A variable pair consists of a base address and a mask indicating the number/location of blocks to be mapped. The registers specify areas of memory and how memory operations should be handled within the area. Typically, they are used to specify writing operation combining for graphic card output but they can also control caching and writeablity.

MTTRs are usually configured initially by the BIOS, then reconfigured by the operating system as needed. On Linux, the MTRRs are mapped into the /proc/mttr psuedo-directory.

Intel MTTRs may specify fixed memory ranges for the first megabyte of memory with several different resolutions.. Any area of memory can be specified in the 8 variable registers using a 4K resolution and if the mapping complies with a set of addressing constraints that are exceptionally byzantine even for Intel. Intel specifies that only 6 variable pairs should be configured permanently so that two pairs will be available for use by the OS. Programmable characteristics include write-combining, No Caching, Write-thru Caching, and Write-back caching. Ranges may be able to overlap if the specifications are not inconsistent. Access to regions not mapped to an MTRR is said to be very slow because caching will not be enabled.

Using MTRRs for write combining can, it is claimed, speed up memory and display operations by as much as 250 percent. It may also slow a few operations slightly.

MTRRs can be used with multiple processors, but areas of shared memory must be configured compatibly on all CPUs in order to maintain cache coherency.*/

Return To Index Copyright 1994-2011 by Donald Kenney.