SDRAM is being implemented on Dual In Line Memory Modules (DIMMs) -- circuit boards similar to the older SIMMs used for DRAM but with different pinouts, pin counts and voltages. Current designs vary from 16 to 512 Megabytes per DIMM.
Determining SDRAM timing is very (and unnecessarily) complex. Unlike DRAM which is speced by "Access" time, SDRAM is specified by a clock rate -- typically 10nSec. This, plus faster bus clocking, makes SDRAM look much faster than DRAM. The truth is that it is only a bit faster and that clock ticks are skipped to make the very fast numbers for SDRAM match the actual capabilities of the chips. One unfortunate result is that some parameters used to describe the number of clock delays are different at different PC clock speeds. This is a complex area. I'll address it in a separate article. For the time being, be warned that DIMMs specified as CAS2 at 66MHz are probably CAS3 at 100MHz. After allowing for an additional RAS to CAS delay, this would be about equivalent to 50 or 60nSec EDO DRAM.
The rating for clock rate (e.g. 7,8 or 10 nSec) determines how fast the bus can be run. The fastest bus will be, at best, the inverse of the clock spec. i.e. 10nSec SDRAM won't run faster than 100MHz and may not run at 100MHz if the lines are too heavily loaded. There is a slight advantage usually to a faster bus due to finer time granularity, but in most cases, A faster bus just means more clocks skipped to make memory run.
Layers refers to the number of copper clad layers in the DIMM. Intel dictates (but can not enforce) the use of six layer circuit boards for SDRAM DIMMs but many vendors feel that cheaper four layer boards can be made to meet Intel PC-100 performance specs. All other things being equal, six layer boards are probably to be preferred.
Buffering/Registered refers to whether buffer registers are used on the DIMM. The registers are locked to the bus clock with a Phase Lock Loop. Heavy duty computers requiring more than 4 DIMMs may need buffered DIMMs. Buffered DIMMS have a small notch between pins 10 and 11 and should have an R at the end of the PC100 ID on the DIMM.
There is an Output Valid delay. 7nSec will work in systems with only 2 DIMMs. 6nSec may be required in larger systems.
3.3 volt compatible PC100 DIMMs have a notch between pins 40 and 41.
There is a space in the middle of the Intel SDRAM layout that is reserved for ECC RAM and is not supposed to be used for anything else. This may be the only way to identify ECC SDRAM visually
SDRAM identification: PC100 compliant DRAMs should be identified on the board as PCX-abc-def-g where
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