PCI BUS

11/15/97

Peripheral Connect Interface Bus: (PCI Bus) Unlike other buses used in IBM compatible PCs, the PCI bus was designed by Intel Corporation to be CPU independent. It was designed as a 33 MHz, 32 bit wide bus. It was later extended to 64 bit width and then to 66 MHz. 3.3 volt operation is supported in the standard. 5 volt and 3.3 volt cards are not interchangeable but there are "universal" cards that can use either voltage. The connectors have notches and keys that prevent insertion of incorrect voltage cards into slots not designed to accept them. Most of the details of the standard have been adhered to other than Bus speed. Although the PCI standard permits CPU operation asynchronous with the data bus, such operation is inefficient because the CPU must usually wait fractional clocks for the bus and vice versa. The bus is frequently operated at non-standard speeds such as 25MHz, 30MHz or 83MHz in order to accommodate CPUs operating synchronously at integer or half integer multiples of the bus speed.

Although theoretical transfer speeds of 133 (33MHz, 32 bit), 266 (33MHz, 64 bit) or 533MHz are very fast, practical data rates are much slower due to wait states and signaling delays. For the most part, the PCI bus will be further slowed due to competing with the CPU for memory access. Practical speeds for 33MHz, 32 bit operation are thought to be comparable with those of VLB -- perhaps a bit slower in 486 machines and a bit faster in Pentium machines. Almost all Pentium and later PCs use the PCI bus.

The PCI bus operation is much more complex than other PC buses. Like VLB, it allows bus mastering where a device other than the CPU provides bus controlling signals. It supports burst mode data transfers that clock data into/out of successive addresses without requiring the bus controlling device to post a new address. Level triggered interrupts that support multiple devices on the same interrupt line are supported. A machine independent interrupt scheme is used that allows PCI cards to operate in non-PC architectures. PCI supports four level triggered interrupts which are mapped to PC IRQs. PCI device drivers are required to support interrupt sharing. Early PCI devices may not fully support all aspects of PCI interrupt handling.

Although the PCI bus is specified to support 10 devices, practical devices usually impose two loads, resulting in a maximum of four PCI slots plus the motherboard in most PCs. A second PCI bus is sometimes bridged in to allow more slots.

PCI supports automatic device configuration (Plug aNd Play) and contains a 256 byte configuration area that identifies card type, status, ROM address (if any), etc. In theory, this allows run time allocation of resources to devices -- however that is largely incompatible with vast amounts of older "legacy" software that requires components to stay in one known location.

PCI will support the automatic configuration of devices, in that registers within the PCI chipset will keep an inventory of available resources (like interrupts) and will allocate a free resource to a new PCI card when inserted.

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