Clock 1 -- CPU posts address Clock 2 -- Memory decodes address Clock 3 -- Source (CPU or memory) posts data Clock 4 -- Destination (memory or CPU) accepts data
The 80286 Introduced separate data and address buses and a pipelined 3 clock data accessing scheme that allowed effective 2 clock data access by overlapping the first operation of one cycle with the last of the previous cycle.
Clock 1 -- CPU posts Address -- Destination (memory or CPU) accepts Data from previous operation. Clock 2 -- Memory decodes address and Source (CPU or memory) posts data (Clock 3) -- (Overlapped with next Clock 1) -- Destination (memory or CPU) accepts Data from previous operation.
The 80486 Introduced internal data caches that often move data in "lines" of 4*32 bit "words". To take advantage of this characteristic, a "burst" read mode was introduced that permitted the last three words of a line to be moved in a single cycle each by overlapping the memory access for one word with the data posting from the previous. In the 486 implementation, the CPU posts only the first address in the "line". subsequent addresses are generated externally in the chipset or (conceptually at least) in the memory. Burst length is determined by the external address generation capability. Some Pentium chipsets support multi-line bursts. Many non-Intel 486 variants -- the 486DLC for example -- do not support burst mode access.
Return To Index Copyright 1994-2008 by Donald Kenney.