SDRAM (Synchronous Dynamic RAM) is becoming the standard Mass memory technology for the late 1990s -- replacing various technologies of unclocked Dynamic RAM. SDRAM is not a revolutionary change in RAM technology. It does include several modest performance improvements and it is revolutionary in the sense of using new packaging -- 168 pin DIMMs -- that use different signaling and are not compatible with older chips and packaging.

SDRAM includes the following features:

1. Use of latest IC memory cell technology permitting access and recovery times for single words around 35 nSec vs 50 or 60 nSec for the fastest available commercial DRAM.

2. Use of an internal architecture that allows performance equivalent to well designed interleaved DRAM memory to be built into the memory module. This removes the burden of optimizing memory from the motherboard designer and makes performance more independent of how many memory modules are installed and how they are configured.

The following features are included:

.Optimization of "Fast Page" access to rows of data retrieved insuring fast access to data read in bursts from consecutive addresses.

.Use of an internal address counter for "bursts" from consecutive addresses. This avoids signaling delays required by DRAM.

.Use of a clock permitting pipelining of data into/out of the memory.

.Removal/improvement of antiglitch circuitry and associated delays required in ordinary DRAM by some older board designs. Termination resistors have also been added on DIMM outputs

.Ability to achieve interleaved, pipelined performance without multiple memory modules and complex circuitry. Among other things, this means smaller capacitive loads which means cleaner waveforms and fewer termination problems.

SDRAM achieves optimum performance when dealing with bursts of consecutive data and has little or no advantage over DRAM when doing true random accessing. Fortunately, cached CPUs, video, disks and network cards tend to do burst operations.

SDRAM is rated in clock time rather than access time. Since initial/random access to SDRAM typically takes 3 to 4 clocks and there are external delays as well, random access times for 10 nSec SDRAM parts are really little, if any, faster than 60nSec DRAM.

Most SDRAMs are capable of handling four clock signals, but some early ones handle only two and will not work with circuits delivering four signals.

Measured performance improvements for SDRAM over EDO DRAM are typically reported to be about 20% yielding a 5% to 10% improvement in overall system performance. Compatibility problems between specific SDRAM modules and specific motherboards have been reported. This seems to be not uncommon with new memory technologies and has, in the past, resolved itself fairly quickly.

Return To Index Copyright 1994-2002 by Donald Kenney.