Synchronous Burst Cache; A cache built using clocked Static RAM and designed to interface directly to 486 and later CPU burst addressing modes. Clocking means that an external signal is used to clock out results. That allows memory activities to be synchronized with the rest of the system. Burst addressing means that the initial address for data read(/write?) is provided by the CPU or chipset, and subsequent addresses are calculated internally by the memory.

Return To Index Copyright 1994-2002 by Donald Kenney.