The subsequent operations require at least 1 clock. Asynchronous, non-pipelined caches are often capable of 3-1-1-1 operation using the conventional 33MHz CPU external clock on 486s. (Cache lines are always 4 "words" although there is no law of man or nature that prevents a different size from being used in future CPUs). Some 486s need 3-2-2-2 clocking. The faster Pentium CPU external speeds of 60MHz and 66MHz require special fast caches capable of accessing data in 15 to 17 nsec per operation including all latching and propagation delays in order to achieve 3-1-1-1. This is often attained by pipelining fast (7nSec) SRAM and locking the DRAM to the CPU clock (synchronous operation) rather than by manipulating the conventional control signals (asynchronous operation). Some Pentium chipsets allow bursting to be extended to consecutive cache lines when consecutive memory lines are read -- combining what might otherwise be multiple 3-1-1-1 bursts into a 3-1-1-1-1-1-... operation. Cache that supports this is known as Synchronous Burst Cache. A frequently asked question is -- "which is faster (pick one or more of "synchronous/ asynchronous", "burst", "pipelined/ nonpipelined") cache or (pick some other combination). It's really not a very meaningful question. The proper questions are "Will the configuration in my machine support 3-1-1-1 clocking?" and "Can the burst be extended?".
NOTE: Two different conventions are used to count clocks. I have chosen to use the convention used by Intel in the early 80x8x documentation which includes a clock used internal to the CPU to route signals to the CPU pins. Motherboard engineers often do not count this clock and count only the clocks visible outside the CPU. One man's 3-1-1-1 cycle may be another's 2-1-1-1. It is usually impossible to determine which convention is being used.
Return To Index Copyright 1994-2008 by Donald Kenney.