The Crusoe CPU uses a Very Long Instruction Word CPU with a non X86 instruction set. In the VLIW architecture, instruction parallelization and serialization must be done in software prior to queuing the X86 emulation code for execution. This results in some performance degradation but removes a large amount of specialized circuitry that is required to support parallelism in conventional superscalar CPUs. To avoid reparallelization overhead in loops, code translated into Crusoe instructions is stored in an instruction cache. Transmeta claims that the Crusoe has about 25% of the transistor count of a conventional CPU with comparable performance. In principle, the Crusoe could emulate other CPUs with non-X86 instruction sets.
Internally, Crusoe has a Floating Point Unit, an integer unit, a load/store unit, and a branch unit. There are 64 renamable integer registers that are used for X86 register emulation as well as for Crusoe operating status.
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